In this field of microelectronics, it is of particular importance to be able to perform transfers of thin layers containing circuits. These transfers of thin layers enable, notably, transfer of the circuits onto wafers different than those that were used to produce them.
For example, these wafers may be semiconductor wafers containing electronic components or wafers having properties different from the substrates that were used to produce the components.
In some cases, it is sought to have access to the rear face of the components, the face that rests on a substrate on which or from which they may have been prepared.
A known technique for doing this is illustrated in FIGS. 1A-1D. It consists of bonding a first wafer 2, on which a treated thin layer 5 is formed on the front face, with a second wafer 8, and thinning or removing its substrate 1 on the rear face.
The first wafer 2, or rather its treated thin layer 5, contains, in particular, some circuits 3, 6 (FIG. 1A).
In preparation for a bonding by molecular adhesion with this second wafer 8, in general, a layer 4 of bonding material is deposited on the front face of the thin layer 5 in order to be leveled off and compatible with direct bonding (FIG. 1A). Lacking such a leveled off layer 4, non-bonded zones (corresponding to zones with a topology on the surface of the circuit) may be present at the bonding interface and interfere with the transfer of the thin layer 5.
The second wafer 8 for its part is surface oxidized (FIG. 1B). Reference numeral 10 designates the surface layer of oxide.
The bonding step can then take place after the adhesive layer 4 has been leveled off (FIG. 1C).
Finally, the portion of the first wafer 2 not containing the treated zone is thinned or removed (FIG. 1D), for example, by planing or by chemical etching (dry or wet). The surface 5′ of the thin layer 5 containing the circuits 3, 6 is then buried at the bonding interface formed by the bonding layer 4.
In some cases, the thin layer 5 is a layer comprising some circuits 3, 6, which may be very elaborate and may, therefore, be of a very high cost. It is not acceptable to be unable to perform the transfer step onto the second wafer 8 with an efficiency that is equal to, or very close to, 100%.
More generally, the simple fact that there is a bonding defect vertically in line with a chip or a component makes it unusable. The defects may be particles that are present on the surface and difficult to clean or defects buried in the oxide layer.
The presence of defects on the leveled off surface, therefore, causes bonding defects, which greatly affect the yield by making some chips unusable.
For example, after the step illustrated in FIG. 1D, a cutting into individual circuits may be performed along cutting lines such as those indicated by the arrows 11 (FIG. 1D). If defects or voids are present at the bonding interface between the adhesive layer 4 and second wafer 8, this may make the whole of the wafer unusable.
The same problem may appear in the case of a surface that is structured but homogeneous (i.e., not comprising multiple layers and materials of different natures), for example, the surface of at least part of the thin layer 5 without circuits 3, 6, this surface having, however, a topology with defects or voids during bonding.
Furthermore, the problem is posed of finding a novel process to ease the carrying out of the transfer of a layer, such as thin layer 5, which may contain some circuits or components and having a surface topology on a support such as second wafer 8.